1. Field of the Invention
The invention relates to semiconductor components and somewhat more particularly to a method of producing dynamic semiconductor memory cells with random access in accordance with double polysilicon gate technology.
2. Prior Art
The double polysilicon gate (Si.sup.2 -gate) process is regarded as a standard process for attainment of dynamic RAM (random access memory) memories. This process, used for production of a dynamic 16,384 bit memory, having random access is described by C. N. Ahlquist et al. in IEEE Journal of Solid State Circuits, Vol. SC-11, (1976) pages 570-573.
As can be derived from S. Matsue et al., Conference Volume, ISCCC 1980, Digest of Technical Papers pages 232-233, a 256 K dynamic RAM memory cell has already been produced with currently attainable structure resolution of approximately 1.5 .mu.m photolithography. Insulation between adjacent active regions (transistors, storage capacitors, diffused zones) is attained by thick oxide regions generated by so-called LOCOS technology. The LOCOS process (local oxidation of silicon) is an insulating method used in producing integrated circuits having high component density. Silicon dioxide (SiO.sub.2) is utilized as the insulating material between the various active regions. After selective deposition of an oxide layer and a nitride layer, a local oxidation occurs in the nitride-free zones, whereby a strong lateral under oxidation (the so-called bird's beak) and a strong lateral out-diffusion of field implantation occur, which result in a great width dependency of the threshold voltage for narrow transistors. LOCOS processes of this type are disclosed by J. A. Appels et al., Philips Research Reports, Vol. 26, No. 3, (1971) pages 157-165. With this insulation technique, minimum structured dimensions cannot be realized for insulation spacing, apparently because of the gradual transitions between thick oxide and thin oxide regions (bird's beak) of approximately 0.5 .mu.m in length. Therefore, the minimum possible insulation spacing for LOCOS insulation is at about twice a bird's beak length above the minimum structural dimension. As a result, in the case of the 256 K-RAM memory cell described by S. Matsue et al., Conference Volume ISCCC 1980, referenced earlier, an additional space requirement of approximately 25% of cell area is required. The larger space requirement for the insulation region causes an enlargement of the overall chip surface. A further basic difficulty in the reduction of insulating spacing occurs because of the so-called short channel effect of a thick oxide transistor. Thick oxide transistor losses inhibit capability for insulation spacing smaller than 2.5 .mu.m.
A. F. Tasch et al., IEEE Journal Of Electron Devices, Vol. ED-25, (1978) pages 33-41 describes a HiC (high capacity) RAM cell design whereby, in order to increase cell capacity, a flat arsenic ion implantation and a deep boron ion implantation are performed in the memory region. With such a double implantation, cell capacity of a 256 K memory cell is increased by approximately 25%.